1. Field of the Invention
This invention pertains in general to a method of fabricating a semiconductor device, and, more specifically, to a method of etching metal oxide trenches.
2. Background of the Invention
In modern integrated circuits (xe2x80x9cICsxe2x80x9d), reduction of feature sizes is an important consideration in lowering manufacturing costs. Photolithography is a pattern transfer technology using a light-sensitive photoresist material and controlled exposure to light. A photoresist is initially applied as a thin film to a silicon substrate and the photoresist is exposed to light through a mask to pattern the photoresist. Photolithography has been a major limiting factor in the continued reduction of feature sizes. One of the feature sizes that must be controlled in the lithographic process is the absolute size of contact dimensions which is referred to as critical dimension (xe2x80x9cCDxe2x80x9d).
During the photolithographic process, light passes through the photoresist film down to the semiconductor substrate, where it is reflected back up through the photoresist. The reflected light could damage the adjacent photoresist, adversely affecting the control of CD. In general, there are two types of light reflectivity problems: reflective notching and standing waves.
It is known that using an anti-reflection coating (xe2x80x9cARCxe2x80x9d) can minimize reflective notching and CD variations caused by standing wave effects. A more common way is the application of an ARC to the wafer surface before the photoresist is applied. The ARC material is capable of suppressing unintended light reflection from a reflective substrate that is beneath the photoresist.
In a general CMOS process flow, photolithography is followed by an etch process. The basic purpose of etching is to precisely replicate the desired pattern on the wafer surface. Referring to FIG. 1a, an ARC layer 102 is provided over a layer 100 that is the subject of the subsequent etching process. A photoresist 104 is provided over the ARC layer 102 and has been defined and developed, wherein the distance xe2x80x9cAxe2x80x9d represents the specified CD for this particular step of the semiconductor manufacturing process.
When an ARC is provided in a manufacturing process, the subsequent etching process must take into account the ARC layer, which may be difficult because the ARC thickness is usually non-uniform. In conventional processes, an etchant with high selectivity has been employed to etch the ARC layer with minimal unintended etching on the dielectric layer provided over the silicon wafer, in the case of a bottom ARC layer (xe2x80x9cBARCxe2x80x9d). The etching process continues to etch the dielectric layer down to a target depth to form trenches.
Although use of the etching material having high ARC to underlying layer etching selectivity is able to overcome the ARC thickness variation issue, an unintended result is that the photoresist exhibits a sharp profile with the space separating adjacent photoresist sections at the top being much wider than at the bottom as shown in FIG. 1b. Consequently, the CD actually etched is much larger than intended and becomes unpredictable as shown in FIG. 1c, wherein the distance xe2x80x9cCxe2x80x9d represents the actual dimension obtained, and wherein xe2x80x9cCxe2x80x9d is greater than xe2x80x9cAxe2x80x9d. Such CD instability often signifies instability in a critical part of the semiconductor manufacturing process, and poor CD control results in undesirable decreases in the yield of the manufacturing process.
In accordance with the invention, there is provided a method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.
Also in accordance with the present invention, there is provided a method for forming a shallow trench isolation that includes providing a semiconductor wafer, providing a dielectric layer over the wafer, depositing an anti-reflective coating layer over the dielectric layer, providing a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, etching the anti-reflective coating layer unmasked by the photoresist structures to remove less than the entire thickness of the anti-reflective coating layer, further etching the anti-reflective coating with nitrogen and hydrogen etchants to remove only the anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially the same as a second distance defining an opening at the top of the trench.
In accordance with the present invention, there is additionally provided a method of etching anti-reflective coatings in a semiconductor device that includes providing a dielectric layer, forming a plurality of vias in the dielectric layer, depositing a layer of anti-reflective coating over the dielectric layer and in the plurality of vias, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, providing an etching having high etching selectivity between the anti-reflective coating layer and the dielectric layer to remove only the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer and at least one of the plurality of vias provided with the anti-reflective coating to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and together with the description, serve to explain the principles of the invention.